Recently, a digital technology has remarkably developed and a demand for a higher-speed operation and a higher accuracy of an A/D conversion apparatus that converts an analog signal to a digital signal has more and more increased. As one technology for implementing a higher-speed operation of the A/D conversion apparatus, the A/D conversion apparatus of a time-interleaved system is employed. In this system, a plurality of A/D conversion circuits (also referred to as “sub-A/D conversion circuits”) are cyclically operated in a predetermined order to achieve equivalently high-speed sampling by an entirety of the plurality of sub-A/D conversion circuits. Assume that the number of the sub-A/D conversion circuits connected in parallel is M. Then, by causing the sub-A/D conversion circuits to respectively perform A/D conversion operations at a sampling frequency of fs/M [Hz] at timings (phases) each shifted just by 1/(fs) [sec], an A/D conversion operation equivalent to a conversion process at a sampling frequency of fs [Hz] can be effectively implemented. That is, an increase in speed of the operation to (M) times the sampling frequency (fs/M [Hz]) of the individual sub-A/D conversion circuit) (M being the number of the sub-A/D conversion circuits connected in parallel) can be implemented.
In the A/D conversion apparatus that performs the process by the sub-A/D conversion circuits, however, error components (variations) such a gain (gain), an offset, and a frequency characteristic among the sub-A/D conversion circuits may increase noise and distortion, and therefore may deteriorate a conversion accuracy of the A/D conversion apparatus as a whole. For this reason, it becomes important to perform calibration for making characteristics uniform among low-speed sub-A/D conversion circuits connected in parallel. In this calibration, compensation is applied to each sub-A/D conversion circuit to make characteristics uniform among the sub-A/D conversion circuits uniform.
As means for calibrating gain (gain) and offset error components among sub-A/D conversion circuits, a reference may be done to description of Patent Document 1, for example. In this calibration method, a sine wave is generated as a training anal for calibration. Then, using the signal of the sine wave, sine curve fitting (fitting the converted waveform data to the sine wave) is performed on a sequence of the converted data for each of a plurality of A/D conversion means (corresponding to each of the sub-A/D conversion circuits) to determine a calibration value for each of the gain, the offset, and a skew. The calibration value is stored in a calibration memory. Then, when normal A/D conversion is performed, data is calibrated in accordance with the calibration value stored in the calibration memory. Alternatively, hardware (such as a DA converter) for gain calibration and offset calibration is provided for each A/D conversion means (circuit), and the calculation values of the gain and the offset from the calibration memory are set in the hardware for the calibrations of the A/D conversion circuit.
As a configuration of a time-interleaved A/D conversion apparatus for deriving a compensation control signal by adaptive processing using a teaching signal (teacher signal) to compensate a DC offset, a conversion gain error, and the like of each A/D converter (corresponding to each sub-A/D conversion circuit), a reference may be made to description of Patent Document 2, for example. Patent Document 2 discloses a configuration where in addition to A/D converters (low-speed high-resolution A/D converters) that perform time-interleaved operation, a high-speed low-resolution A/D converter that operates at a rate same as an equivalent sampling rate obtained by time interleaving is included. An output of the high-speed low-resolution A/D converter is set to the teaching signal that provides basis for conversion of a conversion error. The compensation control signal is calculated by the adaptive signal processing, and an output value of each of the circuits for A/D conversion connected in parallel that perform the time-interleaved operation is compensated.
That is, this configuration includes M first A/D converters ADC 0 to ADC (M−1) (low-speed high-resolution A/D converters) having a sampling rate of FS [Hz] and a resolution of K1 [bit] and a second A/D converter ADC (M) (high-speed low-resolution A/D converter) having a sampling rate of M×FS [Hz] and a resolution of K2<K1 [bit]. The first A/D converters ADC 0 to ADC (M−1) are connected in common to an analog input terminal, and respectively perform A/D conversions in response to M-phase clock signals CLK 0 to CLK (M−1) each delayed in timing (phase) by 1/FS/M [sec]. Then, obtained digital signals SIG 0 to SIG (M−1) are cyclically multiplexed in synchronization with clocks of M×FS [Hz] to obtain a digital signal x[n] having a sampling rate of M×FS [Hz] and a resolution of K1 [bit]. An output signal y[n] is generated by FIR (Finite Impulse Response) linear filtering operation based on an inner product between a vector signal Xv[n] and a weight vector Wv[n] as follows:y[n]=w(1)x[n]+w(2)x[n−1]+w(3)x[n−2]+ . . . +w(N)x[n−(N−1)]  (1)where Xv[n]=(x[n], x[n−1], . . . x[n−1)])T (T indicating transpose), being composed of N signals obtained by delaying the digital signal x[n] by 0 to (N−1) samples, and the weight vector Wv[n]=(w(1), . . . w(N−1), w(N))T, being composed of N elements.
Alternatively, the output signal y[n] is obtained by nonlinear filtering operation described below, obtained by adding a constant term of w0·x0 to the FIR linear filtering operation:y[n]=w0x0+w(1)x[n]+w(2)x[n−1]+ . . . +w(3)x[n−2]+ . . . +w(N)x[n−(N−1)]  (2)
Then, the second A/D converter ADC (M) and the first A/D converters ADC 0 to ADC (M−1) are connected in common to the input terminal to obtain an teaching signal d[n].
A residual signal between the output signal y[n] and the teaching signal d[n] as follows is generated:e[n]=d[n]−y[n]
Then, the residual signal e[n] is multiplied by a gain vector Kv[n], and is then added to the current weight vector Wv[n] to be set to a weight vector Wv[n+M] after sampling of M samples:Wv[n+M]=Wv[n]+Kv[n]×e[n]  (3)
This gain vector Kv[n] is generated by an adaptive algorithm (RLS (Recursive Least Square) algorithm for example, as well as LMS (Least Mean Square) and so forth) that operates such that a square mean value of the residual signal e[n] is minimized, based on the vector signal Xv[n]. DC offsets, conversion gain errors, sampling timing errors, frequency characteristics and so forth of the first A/D converters ADC 0 to ADC (M−1) are compensated.    [Patent Document 1] JP Patent Kokai Publication No. JP-P2003-133954A    [Patent Document 2] JP Patent Kokai Publication No. JP-P2007-150640A